The invention relates to a floating gate memory cell for nonvolatile information storage, a semiconductor memory device having a plurality of memory cells for nonvolatile information storage, and a method for fabricating a floating gate memory cell for nonvolatile information storage.
In the further development of semiconductor memory devices based upon nonvolatile memory mechanisms, the principle of the so-called nonvolatile floating gate memory cell has also been developed. Such a floating gate memory cell for nonvolatile information storage has a floating gate configuration, a source/drain configuration, and a control gate configuration. The floating gate configuration serves for the actual information storage, while the source/drain configuration is configured for access to the floating gate configuration and, thus, for access to the respective information. The control gate configuration is configured for controlling such access to the floating gate configuration and to the information.
What is disadvantageous in the case of existing semiconductor memory devices, memory cells contained therein, and corresponding fabrication methods for semiconductor memory devices or memory cells is that their fundamental concept, from a structural and production engineering standpoint, is based on the provision of a single binary information unit in each individual memory cell. Each memory cell and, thus, each memory location are, thus, occupied only singularly with information and configured accordingly.
It is accordingly an object of the invention to provide a floating gate memory cell, method for fabricating it and semiconductor memory device that overcome the hereinafore-mentioned disadvantages of the heretofore-known devices and methods of this general type and that, in a particularly simple manner, obtains a particularly high information density and, in a particularly reliable manner, modifies and retrieves such information.
With the foregoing and other objects in view, there is provided, in accordance with the invention, a floating gate memory cell for nonvolatile storage of information including at least one of information units and binary bits, including a floating gate configuration for storing the information, the floating gate configuration having floating gates each independently storing the information and, as a result, storing a corresponding plurality of one of the information units and the binary bits independently of one another in the memory cell, a source/drain configuration accessing the floating gate configuration, a control gate configuration controlling access to the floating gate configuration, the control gate configuration having control gates each associated with a respective one of the floating gates, access to the respective one of the floating gates being controlled by each respective one of the control gates, and the source/drain configuration having two source/drain regions jointly provided for the floating gates and the control gates to permit access of all of the floating gates through the two common source/drain regions.
The invention""s floating gate memory cell for nonvolatile information storage is characterized in that the floating gate configuration has a plurality of floating gates, in that each of the floating gates is configured for substantially independent information storage, and in that, as a result a corresponding plurality of information units, in particular, binary bits, can be stored independently in the memory cell.
Thus, in contrast to the prior art, the invention departs from the one-bit concept and, consequently, the floating gate memory cell according to the invention is configured for storing a plurality of information units, in particular, binary bits or the like. Such a characteristic is realized by virtue of the fact that, in contrast to the floating gate memory cell according to the prior art, the floating gate configuration is configured with a plurality of floating gates. In such a case, each of the floating gates is configured for separate and independent information storage independently of the other floating gates. Consequently, by way of example, a respective bit can be written and retrieved, in accordance with an impressed potential state, in each of the floating gates.
Each floating gate can also be configured for taking up more than two charge and/or potential states, thereby, further increasing the information density per floating gate memory cell.
The structure of the floating gate memory cell according to the invention is configured particularly flexibly if, in accordance with another feature of the invention, the control gate configuration has a plurality of control gates, a respective control gate is assigned to a respective floating gate and the access to the assigned floating gate and the information state contained therein is controllable by each control gate. The initially organizational assignment of a respective control gate of the control gate configuration with a respective floating gate of the floating gate configuration results in a particularly flexible control of the access to the information to be stored in the floating gate. The initially organizational and sequence-technical assignment between floating gate and control gate will, advantageously, also be represented in a structural or spatial assignment, in particular, in a particular spatial proximity of the assigned floating gates and control gates with respect to one another.
A further simplification of the floating gate memory cell according to the invention results if the source/drain configuration has two source/drain regions, the source/drain regions are provided jointly for the plurality of floating gates and/or for the plurality of control gates, and all the floating gates can be accessed by the two common source/drain regions.
With regard to a particularly simple fabrication procedure and also with regard to a corresponding functional reliability, the floating gates are configured substantially identically with regard to their geometrical and/or material properties.
For the reliability of the floating gate memory cell according to the invention, on the other hand, the floating gates are disposed and configured in a manner substantially electrically insulated from one another, from the control gates and from the source/drain regions, and in that, in particular, each floating gate in the floating gate memory cell is configured and disposed in a substantially capacitively coupled manner.
Furthermore, it is advantageous that the floating gates are configured substantially identically with regard to their geometrical and/or material properties.
It is further preferred that the control gates are disposed and configured in a manner substantially electrically insulated from one another, from the floating gates, and from the source/drain regions.
In accordance with a further feature of the invention, the floating gates and/or the control gates are composed of a polysilicon material, polycide, metal, and/or the like.
In accordance with an added feature of the invention, the floating gates and the control gates are composed substantially of the same material.
To realize the assignment between the floating gates and the control gates, in accordance with an additional feature of the invention, the mutually assigned floating gates and control gates are in each case configured in direct spatial proximity to one another, and that, in particular, respective intermediate insulation regions are provided in such a case, in particular, in each case an intermediate dielectric between the respectively assigned floating gates and the control gate.
The intermediate dielectric is also referred to as interpoly dielectric and may be, e.g., an NO or ONO structure, i.e., a structure with a configuration including nitride/oxide or oxide/nitride/oxide, respectively.
It is, furthermore, preferred that each floating gate has a first end region and a second end region. The respective first end region is configured and disposed in direct spatial proximity to the first source/drain region and the respective second end region is configured and disposed in direct spatial proximity to the second source/drain region. As a result, in particular, a spatial and/or areal overlap is formed between the floating gates, in particular, between the respective end regions thereof, and the source/drain regions.
In accordance with yet another feature of the invention, there is provided an insulation region, in particular, in the form of a silicon dioxide material, is provided between the respective floating gate, in particular, the end regions thereof and the source/drain regions.
In accordance with yet a further feature of the invention, a main region of the floating gate cell is formed, to be precise as an elevated region, in particular, as a lamella, a web, a burr, or the like, of a semiconductor material region.
In such a case, the main region, in particular, the lamella, advantageously has side regions. Furthermore, in such a case the, in particular, two, floating gates are provided in the region of the side regions, in particular, in a manner lying opposite one another with the main region in between, in particular, in direct spatial proximity thereto with provision in each case of an insulation region toward the main region.
The provision of such a lamellar region with side regions results practically automatically in an electrical insulation and spatial separation between the floating gates to be formed, on one hand, and between the control gates to be formed, on the other hand.
In accordance with yet an added feature of the invention, the source/drain regions are configured asxe2x80x94in particular n+-dopedxe2x80x94regions of the main region, isolated, in particular, by a channel region as part of the main region. Although n-channel transistors are preferred, p-channel transistors are, nevertheless, possible and provided. In such a case, source/drain regions are, then, configured to be p+-doped.
Such a procedure with the configuration as lamella, thus, additionally automatically enables the formation of source/drain regions that are spatially separate from one another and substantially electrically insulated from one another.
Furthermore, by virtue of its linear extent and by virtue of the possibility of disposing a plurality of such lamellae parallel to one another, the lamellar structure enables a particularly simple procedure when configuring a semiconductor memory device with a plurality or multiplicity of floating gate memory cells according to the invention.
Thus, in the case of the invention""s semiconductor memory device having a plurality of memory cells for nonvolatile information storage, the memory cells are configured as floating gate memory cells according to the invention.
In accordance with yet an additional feature of the invention, adjacent memory cells use at least some of the control gates as common control gates.
In accordance with again another feature of the invention, the plurality of memory cells is configured and disposed in a matrix-like manner and on a plurality of substantially identical main regions, in particular, in the form of lamellae, webs, burrs, or the like.
The design and structure of the semiconductor memory device according to the invention is configured particularly advantageously if the main regions are configured and disposed in a manner extending linearly and substantially equidistantly with respect to one another.
In such a case, the main regions, in particular, the lamellae, are provided substantially as columns and/or as rows of the matrix-like configuration of memory cells.
The invention""s method for fabricating a floating gate memory cell for nonvolatile information storage is presented below. A fabrication method of the generic type is used as a basis in this case. In the case of the method of the generic type, a floating gate configuration, a source/drain configuration, and a control gate configuration are provided. The floating gate configuration is configured for the actual information storage. The source/drain configuration is configured for access to the floating gate configuration. The control gate configuration is configured for controlling the access to the floating gate configuration and to the information contained therein.
With the objects of the invention in view, there is also provided a method for fabricating a floating gate memory cell for nonvolatile information storage, including the steps of providing a floating gate configuration for storing information, the floating gate configuration having floating gates each storing the information substantially independently of one another in the memory cell, accessing the floating gate configuration with a source/drain configuration, controlling the access to the floating gate configuration with a control gate configuration having a plurality of control gates, a respective one of the control gates being associated with a respective one of the floating gates, controlling access to the associated one of the floating gates with each respective one of the control gates, providing the source/drain configuration with two source/drain regions jointly associated with the floating gates and the control gates, and making accessible all of the floating gates through the two common source/drain regions.
The invention""s method for fabricating a floating gate memory cell is characterized by configuring the floating gate configuration with a plurality of floating gates, each of the floating gates being configured for substantially independent information storage, and, as a result, a corresponding plurality of information units, in particular, binary bits or the like, can be stored independently of one another in the memory cell.
In accordance with again a further mode of the invention, the control gate configuration is provided having a plurality of control gates, a respective control gate is assigned to a respective floating gate, and the access to the assigned floating gate is configured to be controllable by each control gate.
On the other hand, the source/drain configuration is provided having two source/drain regions, the source/drain regions are provided jointly for the plurality of floating gates and/or for the plurality of control gates, and, as a result, all the floating gates are accessible through the two common source/drain regions.
In accordance with again an added mode of the invention, in each case the floating gates and/or in each case the control gates are configured substantially identically with regard to their geometrical and/or material properties.
It is, furthermore, preferred for the floating gates and/or the control gates to be disposed and configured in a manner substantially electrically insulated from one another from the control gates and/or from the floating gates and from the source/drain regions.
In the case of the floating gates, it is, furthermore, preferred that they are configured and disposed in a substantially capacitively coupled manner in the floating gate memory cell by virtue of these measures.
The floating gates and/or the control gates are preferably formed from a polysilicon material, polycide, metal, and/or the like. In particular, they are formed from the same material.
It is advantageous to configure the control gate in each case with low impedance. By contrast, the floating gates can also have high impedance.
To realize the assignment between the respective floating gates and the respective control gates, the floating gates and control gates that are respectively assigned to one another are provided in direct spatial proximity to one another, and, in such a case, in particular, an intermediate insulation region, in particular, an intermediate dielectric is provided in each case.
Preferably, each floating gate is configured with a first end region and a second end region. The respective first end region is configured and disposed in direct spatial proximity to the first source/drain region and the respective second end region is configured and disposed in direct spatial proximity to the second source/drain region. As a result, in particular, a spatial or areal overlap is formed between the floating gates, in particular, between the respective end regions thereof, and the source/drain regions. Preferably, an insulation region, in particular, in the form of a silicon dioxide material, is, furthermore, formed between the respective floating gates, in particular, the end regions thereof, and the respective source/drain region.
It is particularly preferred that in each case an elevated region, in particular, a lamella, a web, a burr, or the like of a semiconductor material region is formed as main region of the floating gate cell. In such a case, the main region, in particular, the lamella or the like, is formed with side regions. Furthermore, floating gatesxe2x80x94in particular twoxe2x80x94are provided in the region of the side regions, in particular, in a manner lying opposite one another with the main region in between, in particular, in direct spatial proximity thereto with provision in each case of an insulation region toward the main region.
It is particularly advantageous that the source/drain regions are configured as in particular, n+-doped or p+-dopedxe2x80x94regions of the main region, isolated, in particular, by a channel region as part of the main region.
The previous characterizing features of the fabrication method according to the invention represent, in part, the structural features of the floating gate memory cell to be formed according to the invention. However, different configurations are, furthermore, conceivable during the fabrication.
In accordance with again an additional mode of the invention, first, a semiconductor substrate region, in particular, in the form of p-doped silicon, is provided. Local doping regions, in particular, in n+-doped form, are, then, formed for the source/drain regions to be formed, in particular, by implantation. Afterward, the main region for the memory cell is, then, formed by etching back the surroundings in the semiconductor material region, in particular, using a masking process or the like.
It is also possible to use n-doped silicon, in which case p+-doped source/drain regions are to be provided.
The last two steps mentioned can also be carried out with their order reversed so that, first, the main regions, that is to say, in particular, the lamellar structure, is formed by etching back the surroundings in the semiconductor material region, in particular, using a masking process or the like, and, then, doping regions in local form are formed subsequently, in particular, by implantation.
Advantageously, the local doping regions are formed in a first strip form, and the etching back is effected in a second strip form, transversely with respect to the first strip form.
Particularly advantageous structures result if, in accordance with still another mode of the invention, the main region is configured to be linear and/or approximately parallelepipedal. Such a configuration can be effected by skillful process control during etching back.
Then, an insulation layer is formed or deposited substantially conformally, in particular, made of a silicon dioxide material and/or, in particular, for the insulation region between the main region and the floating gates to be formed.
Furthermore, the insulation layer is formed by being grown.
Afterward, a material region is, then, formed, in particular, deposited, for the floating gates to be formed. In such a case, in particular, polysilicon material or the like is used.
Afterward, the floating gates are, then, patterned, in particular, by etching columns into the material region for the floating gates. In such a case, the columns are formed such that they run perpendicularly to the direction of extent of the main region, that is to say, for example, of the lamella. Such a formation is followed by removal or etching back of the material region for the floating gates to a point below the level of a surface region of the main region, for example, of the lamella so that the material region or the material for the floating gates remains only in the region of the side regions of the main region.
Afterward, a material region is formed or deposited substantially over the whole area and/or conformally, in particular, for the intermediate insulation region to be formed between assigned floating gates and control gates.
Afterward, a material region is formed or deposited substantially over the whole area and/or conformally, in particular, for the control gates to be formed.
Afterward, the control gates are patterned, in particular, by etching columns that run substantially perpendicularly to the extent of the main region, and by subsequent removal or etching back of the material region for the control gates to a point below the level of the surface region of the material region for the intermediate insulation region so that the material region for the control gates remains only in the region of the side regions of the main region, in particular, the material region for the intermediate insulation region not being removed.
Preferably, the structure so obtained is embedded in an insulation region and subsequently formed with a contact connection to the source/drain regions and/or the control gates.
The above-described and further aspects of the present invention are also explained based upon the remarks in the following text:
In flash memory cells, it is possible to store a plurality of bits per cell by storing different charge states or by storing a respective bit at spatially separate locations. However, the last-mentioned possibility has, hitherto, necessitated the use of a so-called charge-trapping device. This means, for example, that the charge is stored in a nitride layer.
The present invention presents a different approach, in which a floating gate cell can be realized for storing two or more bits in one cell.
The storage of two bits in one flash cell has been realized, heretofore, either by the use of an Si3N4 layer (NROM concept). Floating gate cells have, heretofore, used exclusively the storage of a plurality of charge states in a floating gate for storing a plurality of bits in one cell.
By fabricating Si lamellae, it is possible to realize a floating gate cell that has two floating gates but is supplied through the same source and drain regions. As a result, one or even a plurality of bits can be stored in each of the two floating gates.
A core idea is that the channel of the transistor is shifted from the Si surface to the surface of an Si lamella. Such shifting makes it possible to provide a respective floating gate at two locations of the lamella and, thus, to store two or more bits in the cell.
The function of the memory cell is explained in the following text.
If the component, that is to say, the floating gate memory cell, is processed in the manner described below, then an inversion channel can be produced at the left-hand and right-hand sides of the component both with the first control gate and with the second control gate. Each of these channels can be utilized as a separate memory cell area because the gate voltage can be set separately for each side of the component during programming and erasure.
During programming, the methods are possible by hot electrons or by Fowler-Nordheim tunneling. During erasure, it is possible to have recourse substantially to Fowler-Nordheim tunneling from the floating gate either to source, drain, or channel (or a combination). The programming by hot electrons can be carried out either jointly for both bits or separately for each bit.
It is an important innovation in the case of such a component that, although two gate regions are available for storage and driving, they are supplied only by in each case a common source/drain region.
The fabrication of a memory cell according to the invention is described in the following text.
The incorporation of a memory cell into an array is possible in a plurality of architectures (common ground NOR, virtual Ground NOR etc.). The latter differ in each case by the extent to which one of the source/drain regions is additionally utilized by further cells and, therefore, if appropriate, need not be separately contact-connected. The incorporation into different array architectures is effected analogously to conventional flash cells. Equally, the contact connection of the control gates is not described below. Such a contact connection is effected, in principle, at the array edge, and both control gates can be contact-connected on one side, or the control gates can be contact-connected on respectively opposite sides of the array.
Other features that are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a floating gate memory cell, method for fabricating it and semiconductor memory device, it is, nevertheless, not intended to be limited to the details shown because various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof, will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.